A current common requirement for an advanced electronic circuit and particularly for circuits manufactured as integrated circuits (“ICs”) in semiconductor processes is the use of a pillar or column over an integrated circuit terminal to form a column or pillar solder bump or solder column connections. In a traditional “flip chip” approach to packaging and interconnections, solder bumps are used to couple the external terminals of a monolithic integrated circuit (which may be a silicon substrate with active or passive circuit elements and connections formed upon it, or other semiconductor substrate materials including gallium arsenide (GaAs), silicon on insulator (SOI), and silicon germanium (SiGe)) to a package substrate or circuit board. Sometimes an interposer is also incorporated and the integrated circuit is mounted to the interposer, which in turn is mounted to the circuit board or package substrate. As is known in the art, interposers may be used to provide improved thermal matching to the die and stress relief These integrated circuit devices may have tens or hundreds of input and output terminals for receiving and sending signals and/or for coupling to power supply connections. In some IC designs, the terminals are placed at the periphery of the integrated circuit and away from the active circuitry. In more advanced and complex integrated circuits, the terminals may be placed over the active area and lie over the active devices within the integrated circuit. In memory integrated circuits, sometimes a center pad arrangement is used.
In a “flip chip” application, the integrated circuit (IC) is mounted face down (flipped) with respect to the substrate. Terminal openings are formed in a protective insulating layer overlying the wafer including the integrated circuit, called a passivation layer, which overlies the face of the integrated circuit device. Conductive input/output terminals of the integrated circuit are exposed in these openings. Solder (including lead free solder material) bumps; solder columns or solder balls are placed on these terminals. The solder bumps may be formed as hemispherical shapes or columns of conductive material extending away from the surface of the integrated circuit. The solder bumps or columns are then used to form the external connections to the integrated circuit. The solder bumps may be provided already formed on the completed integrated circuit using a “wafer scale” or wafer level process approach, or the solder connectors may be added later after the wafers are singulated into individual integrated circuit devices called “dice”. Presently, wafer level bumping operations are increasingly preferred.
In any case, a thermal solder reflow process is typically used to cause the solder bumps to melt and then reflow to complete the mechanical and electrical connection between the flip chip integrated circuit and a substrate. The substrate may be resin or epoxy, a laminated board, film, printed circuit board or even another silicon device. In thermal reflow, the solder bumps, solder balls, or solder columns, which may be lead based or lead free solder, melt and then cool to form a permanent mechanical, and electrically conductive, connection between the terminals of the integrated circuit and the substrate. The combined flip chip IC and substrate may then be packaged as a single integrated circuit. Typically, these flip chip packages are completed as ball grid array or pin grid array packages. Alternatively, in a multiple chip module form, the flip chip may be combined with other integrated circuits which may also be “flip chips”, or wire bond connections may be used. For example, sometimes memory devices such as FLASH nonvolatile devices, and processors that would use the FLASH device for program or data storage, are combined in a single packaged device. IC devices may be stacked vertically or placed alongside one another using a larger substrate, interposer or circuit board.
In current wafer level processing, the wafer is typically bumped using wafer scale processes. The wafer is processed as a unit at least until the solder bumps are completely formed on each device on the wafer, and then a singulation process may be performed to separate the integrated circuits as individual dice or dies. The bumped dies are individually processed after that. In a flip chip application, the dies are flipped over to face a package substrate or interposer, and the solder bumps are aligned with solder pads on the substrate, a thermal reflow process completes the assembly by causing the solder bumps to melt and make an electrical and mechanical connection between terminals on the die and the terminals on the substrate. The assembly process often includes adding an underfill (“UF”) material after reflow, to further protect the solder connections during thermal cycles that are expected in use of the device.
As the industry advances wafer level processing (WLP) further, the package steps performed at the wafer level are increasing so that the number of steps to be performed on individual dice is decreasing; however, a variety of different wafer level and die process level steps are currently in use.
Recently, the semiconductor industry has been moving to “lead (Pb) free” packaging and lead-free device connector technology. This trend increasingly results in the use of lead free solder bumps and lead free solder balls to form connections with integrated circuits and packages. These lead free solder materials are formed of tin and tin alloys which may include, for example, silver, nickel, copper and other metals. The lead-free composition is a eutectic, that is, the materials in it have a common melting point. The use of lead free solder is safer for the environment, safer for workers in the industry and safer for consumers than lead based solder bumps or solder balls. However, the quality and reliability of the final solder connections formed has not always been as great as desired.
In addition, as device sizes continue to fall, the pitch between the terminals on the integrated circuits is also decreasing. Bridging between adjacent bumps may cause electrical shorts, for example. Also, the solder bumps are subject to mechanical deformation so that the bump heights in a completed flip chip substrate assembly may be non-uniform and the bumps may, after remelting and reflow processing, end up with unequal distances between them. Further, the use of underfills (“UF”) with solder bumps in certain fine pitch devices can leave voids in the UF materials, creating additional problems such as cracking and hot spots, etc.
A solution for finer pitch devices is to use, instead of solder bumps, copper or other conductive pillars with a solder (typically a lead free solder) cap. In addition to copper (Cu), other conductive materials such as nickel (Ni), gold (Au), palladium (Pd) and the like may be used, and alloys of these metals may also be used. These pillars form a connector type referred to as “copper pillar bumps”. Copper pillar bumps may also include copper alloys and other copper containing conductors, or the pillar bumps may be formed of other conductive materials. An advantage of these pillar bumps is that the pillars do not completely deform during reflow. While the solder cap forms a spherical tip that does melt during thermal reflow, the columnar pillar tends to maintain its shape. The copper pillars are more conductive thermally than the solder bumps used previously, enhancing heat transfer. The narrow pillars may then be used in a finer pitch array than previously possible with solder bumps, without bridging shorts, and other problems such as non-uniform bump height. As the size of the integrated circuit devices continues to shrink, the pitch between the terminals and the corresponding pitch between pillar bumps will also continue to decrease. The problems associated with the thermal stresses observed using pillar bumps may be expected to increase with continued reduction in the pitch between terminals.
The drawings, schematics and diagrams are illustrative and not intended to be limiting, but are examples of embodiments of the disclosure, are simplified for explanatory purposes, and are not drawn to scale.